1. Field of the Invention
This invention relates to a method of fabricating semiconductor devices and more specifically to annealing process of an oxide layer for use during the fabrication of semiconductor devices and more particularly to a post annealing process for an oxide layer formed using TEOS followed by a chemical-mechanical polish process or etch back process.
2. Description of the Prior Art
Very Large Scale Integrated (VLSI) and Ultra Large Scale Integration (ULSI) circuits utilize a variety of devices having different feature sizes or device dimensions. Such devices include, but are not limited to, transistors, diodes, capacitors, resistors and wires. The minimum state of the art device dimensions have shrunk to the submicron level.
Some devices may have submicron feature sizes while others may simultaneously have much greater feature sizes. Shallow trenches of constant height and varying widths are used to isolate individual devices. These trench widths can vary greatly. These trenches are typically filled with a dielectric material, such as silicon oxide. Because of the complex topography, especially when shallow trenches of greatly varying widths are used, a problem often encountered is achieving a uniform oxide fill, in those trenches, independent of trench size and device density.
In addition, steps, trenches and other topography changes occur across the wafer in scribe areas and near the wafer edges. For such VLSI and ULSI circuits, topology management during fabrication has become a critical process step.
As feature sizes or device dimensions are scaled downward, more stringent requirements on deposition, photo, and etching processing are posed. Surface-clearing planarization processes, such as are used to create oxide-filled trench isolation, often require that the planarized material thickness be controlled to within a very tight tolerance. When simultaneously achieved over all topographies this condition is referred to as "global" planarization. As compared to conventional Local Oxidation of Silicon (LOCOS) isolation, shallow trench isolation (STI) offers improved isolation between devices and greater packing density. Additionally STI offers a higher degree of planarity, which becomes increasingly important as the photolithographic depth of focus budget continues to shrink with decreasing minimum line width.
A common method for planarizing steps in surface topology is a chemical-mechanical polish (CMP) process. This CMP process sequence is as follows. The isolation trenches are patterned onto a Semiconductor wafer or substrate, generally a silicon substrate. Oxide is deposited conformally onto the wafer with patterned trenches. CMP is used to polish the oxide back to the silicon nitride that caps the active area mesas.
However, the inventor has found that a problem exists in forming the Silicon nitride (SiN) chemical-mechanical polish (CMP) stop layers. After the CMP step, some silicon nitride (SiN) remains (called SiN residues) occur in certain areas of the wafer, such as near the scribe line, wafer edge and peripheral area. The silicon nitride and oxide in these areas will peel after subsequent thermal steps and will cause particle contamination. These particles degrade product yields by degrading subsequent photoresist coating processes. If the peeling regions occur cross contact areas, they will cause contact failure which will decrease the yield.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following U.S. patents. U.S. Pat. No. 5,494,857 (Cooperman) shows a method of chemical-mechanical polishing (CMP) using a silicon nitride stopper layer. U.S. Pat. No. 5,334,554 (Lin) shows a method of using a nitrogen plasma treatment on dielectric layers. U.S. Pat. No. 5,296,411 (Gardner) shows a N.sub.2 anneal for a tunnel oxide. U.S. Pat. No. 5,635,425 (Chen) shows a N.sub.2 Plasma treatment for BPSG and PSG layers prior to the TEOS-Oxide deposition. U.S. Pat. No. 5,474,955 (Thakur) shows a method of annealing an oxide layer.
Accordingly, although various improvements in planarization techniques have been developed, manufacturability problems still exist related to the peeling of the silicon nitride (SIN) planarization stop layer and oxide layer.